diff options
| author | Sergey Shtylyov <[email protected]> | 2021-03-12 23:43:46 +0300 |
|---|---|---|
| committer | David S. Miller <[email protected]> | 2021-03-12 17:50:42 -0800 |
| commit | bc9d992ca4d240657dba8fe722ce327bd743b35f (patch) | |
| tree | b11c5bf60208514c554cb679e9b8ea94d72a36b3 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 7c678829efa89e23a8556f5e4d9621c51995fb6e (diff) | |
sh_eth: rename TRSCER bits
In all the SoC manuals the TRSCER register bits match the corresponding
EESR registers's bits, but only on the R-Car gen2 SoC those are named
RINT<n> and TINT<n>. Follow the suit and rename the *enum* tag/entries
from DESC_I_* to TRSCER_*.
Signed-off-by: Sergey Shtylyov <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions