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| author | Olivier Dautricourt <olivier.dautricourt@orolia.com> | 2021-06-17 21:53:18 +0200 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2021-07-28 12:25:10 +0530 |
| commit | af2eec750281e581a16b6449b83ce5e994b79d89 (patch) | |
| tree | 4199de2902288ebdf2ab3383ad9b5130fa355d1d /tools/perf/scripts/python/stackcollapse.py | |
| parent | 4aece33cacf726d34ecd8824aee369652ec2beec (diff) | |
dmaengine: altera-msgdma: make response port optional
The response slave port can be disabled in some configuration [1] and
csr + MSGDMA_CSR_RESP_FILL_LEVEL will be 0 even if transfer has suceeded.
We have to only rely on the interrupts in that scenario.
This was tested on cyclone V with the controller resp port disabled.
[1] https://www.intel.com/content/www/us/en/programmable/documentation/sfo1400787952932.html
30.3.1.2
30.3.1.3
30.5.5
Fixes: https://forum.rocketboards.org/t/ip-msgdma-linux-driver/1919
Signed-off-by: Olivier Dautricourt <olivier.dautricourt@orolia.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Link: https://lore.kernel.org/r/8220756f2191ca08cb21702252d1f2d4f753a7f5.1623898678.git.olivier.dautricourt@orolia.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions