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| author | Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> | 2018-11-20 16:31:48 +0100 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2019-01-07 09:53:11 +0530 |
| commit | ae809690b46a71dc56cda5b3b8884c8c41a0df15 (patch) | |
| tree | bedeeefafb4c153660382cab7f730b48a96af886 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 7df54dbeb055229f6689161aa90bf00bf4af077e (diff) | |
dmaengine: xilinx_dma: program hardware supported buffer length
AXI-DMA IP supports configurable (c_sg_length_width) buffer length
register width, hence read buffer length (xlnx,sg-length-width) DT
property and ensure that driver doesn't program buffer length
exceeding the supported limit. For VDMA and CDMA there is no change.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Andrea Merello <andrea.merello@gmail.com> [rebase, reword]
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions