diff options
| author | Gabriel Fernandez <[email protected]> | 2017-03-16 09:16:41 +0100 |
|---|---|---|
| committer | Michael Turquette <[email protected]> | 2017-04-12 18:50:56 +0200 |
| commit | ac03d8b3a592a0b562fce2376030baf9a572f7c1 (patch) | |
| tree | edabb6be5fc1fa580b0a7d7c61f141f93d263980 /tools/perf/scripts/python/stackcollapse.py | |
| parent | d5a0945fdf89ad293ccaa2be588635f4bfc0cd62 (diff) | |
clk: stm32f4: fix timeout management for pll and ready gate
Use a classic polling to test bit ready.
And the shift of the bit ready of LSE & LSI were wrongs.
Fixes: 861adc44d290 ("clk: stm32f4: Add LSI & LSE clocks")
Signed-off-by: Gabriel Fernandez <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Signed-off-by: Michael Turquette <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions