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authorAnnaliese McDermond <[email protected]>2019-03-21 17:58:47 -0700
committerMark Brown <[email protected]>2019-03-25 15:53:47 +0000
commita51b50062091619915c5155085bbe13a7aca6903 (patch)
tree63256be3e440a3b5eff50693286302be13777a27 /tools/perf/scripts/python/stackcollapse.py
parentfd2df3aeafa4b4cc468d58e147e0822967034b71 (diff)
ASoC: tlv320aic32x4: Model DAC/ADC dividers in CCF
Model and manage DAC/ADC dividers as components in the Core Clock Framework. This should allow us to do some more complex clock management and power control. Also, some of the on-board chip clocks can be exposed to the outside, and this change will make those clocks easier to consume by other parts of the kernel. Signed-off-by: Annaliese McDermond <[email protected]> Signed-off-by: Mark Brown <[email protected]>
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