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| author | Vandita Kulkarni <[email protected]> | 2019-07-30 13:06:44 +0530 |
|---|---|---|
| committer | Uma Shankar <[email protected]> | 2019-08-08 18:37:50 +0530 |
| commit | 960e9836f7217c682ef6cf4038c7271ab401cc7d (patch) | |
| tree | 28f137ad7831543a8f462fd042bf3cb73f3ecb6d /tools/perf/scripts/python/stackcollapse.py | |
| parent | 3522a33a2746b519b27a675639ac976c9189d1de (diff) | |
drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl
Latency programming remains same as that of ICL and
setting latency otimization for PCS_DW1 lanes is same as
that of EHL, hence extending it to TGL.
Signed-off-by: Vandita Kulkarni <[email protected]>
Reviewed-by: Uma Shankar <[email protected]>
Signed-off-by: Uma Shankar <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions