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| author | Marek Vasut <[email protected]> | 2017-01-12 02:03:23 +0100 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2017-01-20 16:09:22 -0800 |
| commit | 9044d87377b3edbd06468a93818f0609d640c238 (patch) | |
| tree | 6bb17744039a987a7aa43396a5294f101d5b7cc4 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 060982670bf5cf09968e2fd8dd21872dfaf34c82 (diff) | |
clk: vc5: Add bindings for IDT VersaClock 5P49V5923 and 5P49V5933
Add bindings for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips.
These are I2C clock generators with optional clock source from
either XTal or dedicated clock generator and, depending on the
model, two or more clock outputs.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Michael Turquette <[email protected]>
Reviewed-by: Laurent Pinchart <[email protected]>
Acked-by: Rob Herring <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions