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| author | Gabriel Feceoru <[email protected]> | 2016-01-22 13:28:45 +0200 |
|---|---|---|
| committer | Daniel Vetter <[email protected]> | 2016-02-10 08:29:34 +0100 |
| commit | 8c448cadd4dd1bb3a8f34a93eaceb464d6e7a1db (patch) | |
| tree | a24fb7cb9f7c5f48b8c5bf3f68c75dbcc501474c /tools/perf/scripts/python/stackcollapse.py | |
| parent | da3b891b0fb88605bb2d16adaf1ef2a1f16403ba (diff) | |
drm/i915: Handle PipeC fused off on IVB/HSW/BDW
Some Gen7/8 production parts may have the Display Pipe C fused off.
In this case, the display hardware will prevent the enable bit in
PIPE_CONF register (for Pipe C) from being set to 1.
Fixed by adjusting pipe_count to reflect this.
v2: Rename HSW_PIPE_C_DISABLE to IVB_PIPE_C_DISABLE as it already exists
on ivybridge (Ville)
v3: Remove unnecessary MMIO read, correct the description (Damien)
v4: Be more specific in description (Patrick)
Signed-off-by: Gabriel Feceoru <[email protected]>
Reviewed-by: Patrik Jakobsson <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions