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| author | Eugen Hristev <[email protected]> | 2020-11-19 17:43:09 +0200 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2020-12-19 11:50:55 -0800 |
| commit | 83d002877365afac2cb65ef4ad36b445652ebda3 (patch) | |
| tree | de4f1b720675fb84b978060e62c5cb670762fe08 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 3d86ee17d4670406d07f92da6fa4f2aa82cdc5a2 (diff) | |
clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT
Allow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock
from phandle in DT.
Suggested-by: Claudiu Beznea <[email protected]>
Signed-off-by: Eugen Hristev <[email protected]>
[[email protected]: adapt commit message, add CPU PLL]
Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions