diff options
| author | Shuicheng Lin <shuicheng.lin@intel.com> | 2024-01-02 01:02:31 +0000 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2024-01-02 10:09:26 -0800 |
| commit | 835e4d9bb3a13879031942ca6692d5a82ec00158 (patch) | |
| tree | e5ddbf7eba1b9586f6ef2d33b18d85c184801fcd /tools/perf/scripts/python/stackcollapse.py | |
| parent | aa253baca534357e033bd29b074ce1eade2a9362 (diff) | |
drm/i915/guc: Change wa and EU_PERF_CNTL registers to MCR type
Some of the wa registers are MCR register, and EU_PERF_CNTL registers
are MCR register.
MCR register needs extra process for read/write.
As normal MMIO register also could work with the MCR register process,
change all wa registers to MCR type for code simplicity.
Signed-off-by: Shuicheng Lin <shuicheng.lin@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240102010231.843778-1-shuicheng.lin@intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions