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authorFancy Fang <chen.fang@nxp.com>2019-10-28 08:07:59 +0000
committerShawn Guo <shawnguo@kernel.org>2019-10-28 19:32:37 +0800
commit72b2429d40d878bfdd066b9401c9a5cbb2a755d3 (patch)
treeb6332377945fa655317bafa2cb4eaa0b134cb600 /tools/perf/scripts/python/stackcollapse.py
parent8f5d481959a04ad81cc928c698ebe6a9dae23971 (diff)
clk: imx7ulp: do not export out IMX7ULP_CLK_MIPI_PLL clock
The mipi pll clock comes from the MIPI PHY PLL output, so it should not be a fixed clock. MIPI PHY PLL is in the MIPI DSI space, and it is used as the bit clock for transferring the pixel data out and its output clock is configured according to the display mode. So it should be used only for MIPI DSI and not be exported out for other usages. Signed-off-by: Fancy Fang <chen.fang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
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