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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-02-03 17:06:33 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-02-08 09:45:58 +0100 |
| commit | 726fd781195dc99cdcb60b2678694bfa5ccd1825 (patch) | |
| tree | 08de0c41c6443a6bda50110a619f802b524932cb /tools/perf/scripts/python/stackcollapse.py | |
| parent | 81a27b1f69022174567e8237d3de2534821671ba (diff) | |
arm64: dts: renesas: rzg2l-smarc: Add common dtsi file
RZ/{G2L,V2L} and G2LC SoC use the same carrier board, but the SoM is
different.
Different pin mapping is possible on SoM. For eg:- RZ/G2L SMARC EVK
uses SCIF2, whereas RZ/G2LC uses SCIF1 for the serial interface available
on PMOD1.
This patch adds support for handling the pin mapping differences by moving
definitions common to RZ/G2L and RZ/G2LC to a common dtsi file.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220203170636.7747-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions