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author | Kristina Martsenko <[email protected]> | 2017-12-13 17:07:18 +0000 |
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committer | Catalin Marinas <[email protected]> | 2017-12-22 17:35:21 +0000 |
commit | 529c4b05a3cb2f324aac347042ee6d641478e946 (patch) | |
tree | 2fab0e91f3abe37f2b7ee29a02e0c41af6ad03d6 /tools/perf/scripts/python/stackcollapse.py | |
parent | 787fd1d019b269af7912249231dfe34a5fe3e7c8 (diff) |
arm64: handle 52-bit addresses in TTBR
The top 4 bits of a 52-bit physical address are positioned at bits 2..5
in the TTBR registers. Introduce a couple of macros to move the bits
there, and change all TTBR writers to use them.
Leave TTBR0 PAN code unchanged, to avoid complicating it. A system with
52-bit PA will have PAN anyway (because it's ARMv8.1 or later), and a
system without 52-bit PA can only use up to 48-bit PAs. A later patch in
this series will add a kconfig dependency to ensure PAN is configured.
In addition, when using 52-bit PA there is a special alignment
requirement on the top-level table. We don't currently have any VA_BITS
configuration that would violate the requirement, but one could be added
in the future, so add a compile-time BUG_ON to check for it.
Tested-by: Suzuki K Poulose <[email protected]>
Reviewed-by: Suzuki K Poulose <[email protected]>
Reviewed-by: Marc Zyngier <[email protected]>
Tested-by: Bob Picco <[email protected]>
Reviewed-by: Bob Picco <[email protected]>
Signed-off-by: Kristina Martsenko <[email protected]>
[[email protected]: added TTBR_BADD_MASK_52 comment]
Signed-off-by: Catalin Marinas <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions