diff options
| author | Ben Shelton <[email protected]> | 2020-11-20 16:39:33 -0800 |
|---|---|---|
| committer | Tony Nguyen <[email protected]> | 2021-02-08 16:27:01 -0800 |
| commit | 4f8a14976aa4b3304e83ff9b4e0a466a3131df3c (patch) | |
| tree | 2cedd9bfe03e46459e0aa8b5ff1396a8471e6548 /tools/perf/scripts/python/stackcollapse.py | |
| parent | b126bd6bcd6710aa984104e979a5c930f44561b4 (diff) | |
ice: Use PSM clock frequency to calculate RL profiles
The core clock frequency is currently hardcoded at 446 MHz for the RL
profile calculations. This causes issues since not all devices use that
clock frequency. Read the GLGEN_CLKSTAT_SRC register to determine which PSM
clock frequency is selected. This ensures that the rate limiter profile
calculations will be correct.
Signed-off-by: Ben Shelton <[email protected]>
Tested-by: Tony Brelinski <[email protected]>
Signed-off-by: Tony Nguyen <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions