diff options
| author | shaoyunl <[email protected]> | 2020-04-27 13:38:28 -0400 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2020-05-01 15:19:08 -0400 |
| commit | 43a10b15d44221371126a07347f2b5d11b8314df (patch) | |
| tree | fbfc915eaa3d55e2757290c629d9e1b91c5533c1 /tools/perf/scripts/python/stackcollapse.py | |
| parent | d09f85d52ad6d1da9d6b8aecca6b81e0b4750afb (diff) | |
amd/amdgpu: Limit rlcg write registers only for nv12
Create gfx_v10_0_rlc_funcs_sriov for nv12 with rlcg_write function pointers be initialized
so driver can use RLCG to write aceess CSIB and CP_ME_CNTL registers when nv12 in sriov mode
Signed-off-by: shaoyunl <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions