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| author | Dinh Nguyen <[email protected]> | 2022-01-25 10:18:20 -0600 |
|---|---|---|
| committer | Greg Kroah-Hartman <[email protected]> | 2022-02-11 11:15:22 +0100 |
| commit | 3d8d3504d23351bcbab7be08f82c5dfabc3c9e0a (patch) | |
| tree | cfbe55ec68d95019f5a02608002ba9026831740c /tools/perf/scripts/python/stackcollapse.py | |
| parent | 56f26f177b26de041edef245562b68eb857093fc (diff) | |
usb: dwc2: Add platform specific data for Intel's Agilex
The DWC2 IP on the Agilex platform does not support clock-gating.
Acked-by: Minas Harutyunyan <[email protected]>
Signed-off-by: Dinh Nguyen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions