clk: tegra: Define Tegra210 DMIC sync clocks

Tegra210 has 3 DMIC inputs which can be clocked from the recovered clock
of several other audio inputs (eg. i2s0, i2s1, ...). To model this, we
add a 3 new clocks similar to the audio* clocks which handle the same
function for the I2S and SPDIF clocks.

Signed-off-by: Peter De Schrijver <[email protected]>
Reviewed-by: Mikko Perttunen <[email protected]>
Tested-by: Mikko Perttunen <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>

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