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authorMatt Roper <[email protected]>2021-07-21 15:30:36 -0700
committerMatt Roper <[email protected]>2021-07-22 09:29:08 -0700
commit1f3e84c4edcd357eeb608d709c9c2dcb3193c841 (patch)
tree54e22070dbef14f4f97be39046c4b3fe31e289d3 /tools/perf/scripts/python/stackcollapse.py
parent3176fb663c0b0ea5d3edd179cb1252f680e55fbf (diff)
drm/i915/dg2: Add cdclk table and reference clock
Note that DG2 only has a single possible refclk frequency (38.4 MHz). v2: - Drop two now-unused cdclk entries Bspec: 54034 Cc: Lucas De Marchi <[email protected]> Signed-off-by: Anusha Srivatsa <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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