diff options
| author | Fabrizio Castro <[email protected]> | 2024-09-30 15:52:40 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2024-10-09 13:39:13 +0200 |
| commit | 1d930d4bf8e68c2a7122a6d0899a99f0370c45b1 (patch) | |
| tree | ef7e293c9fbfb756d697b196c8c10d3c4ecd14fb /tools/perf/scripts/python/stackcollapse.py | |
| parent | a8130323587cea11e7f15ca7803f1b138d6683d5 (diff) | |
pinctrl: renesas: rzg2l: Remove RZG2L_TINT_IRQ_START_INDEX
The RZ/V2H(P) SoC has 16 IRQ interrupts, while every other SoC has 8,
and this affects the start index of TINT interrupts (1 + 16 = 17, rather
than 1 + 8 = 9).
Macro RZG2L_TINT_IRQ_START_INDEX cannot work anymore, replace it with a
new member within struct rzg2l_hwcfg.
Signed-off-by: Fabrizio Castro <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Tested-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions