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| author | Inochi Amaoto <inochiama@outlook.com> | 2024-03-09 17:02:56 +0800 |
|---|---|---|
| committer | Inochi Amaoto <inochiama@outlook.com> | 2024-04-11 15:37:50 +0800 |
| commit | 18e8c6d2cced6c57d62813f49b57eeb8ee02f984 (patch) | |
| tree | 5c7ff1e007321d85145591d5758865e28940587b /tools/perf/scripts/python/stackcollapse.py | |
| parent | bb7b3419627eb34f3466022d1f4b3c942c09712d (diff) | |
riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC
Add missing clocks of uart node for CV1800B and CV1812H.
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/IA1PR20MB4953198222C3ABC2A2B6DE21BB262@IA1PR20MB4953.namprd20.prod.outlook.com
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions