Merge patch series "riscv: Per-thread envcfg CSR support"

Samuel Holland <[email protected]> says:

This series (or equivalent) is a prerequisite for both user-mode pointer
masking and CFI support, as both of those are per-thread features and
are controlled by fields in the envcfg CSR. These patches are based on
v1 of the pointer masking series[1], with significant input from both
Deepak and Andrew.

[1]: https://lore.kernel.org/linux-riscv/[email protected]/

* b4-shazam-merge:
  riscv: Call riscv_user_isa_enable() only on the boot hart
  riscv: Add support for per-thread envcfg CSR values
  riscv: Enable cbo.zero only when all harts support Zicboz

ink: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>

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