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| author | Jonathan Cameron <[email protected]> | 2022-05-08 18:56:47 +0100 |
|---|---|---|
| committer | Jonathan Cameron <[email protected]> | 2022-06-14 11:53:17 +0100 |
| commit | 0bb5675befe666eeed71ad808426cf2ec1c9a714 (patch) | |
| tree | 465622e166c0d1c8b6c4a77ff94ed63d2831dcc3 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 389b8972eb2a614cb3189e5fa55b1b7f66142c71 (diff) | |
iio: frequency: adf4371: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes: 7f699bd14913 ("iio: frequency: adf4371: Add support for ADF4371 PLL")
Signed-off-by: Jonathan Cameron <[email protected]>
Acked-by: Nuno Sá <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
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