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| author | Peng Fan <peng.fan@nxp.com> | 2022-06-15 21:00:08 +0800 |
|---|---|---|
| committer | Jassi Brar <jaswinder.singh@linaro.org> | 2022-08-02 15:09:54 -0500 |
| commit | 095730dd4ca5fe078fd07db5be68b3026d4ae48a (patch) | |
| tree | d0b68c51ac42a6b20442d6883381d2b7d0f03d8f /tools/perf/scripts/python/stackcollapse.py | |
| parent | 60545466180e791827c84795e7b4828dbeb9e061 (diff) | |
dt-bindings: mailbox: imx-mu: add RST channel
i.MX MU has a MUR bit which is to reset both the Processor B and the
Processor A sides of the MU module, forcing all control and status
registers to return to their default values (except the BHR bit in the ACR
register and BHRM bit in BCR register), and all internal states to be
cleared.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions