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| author | Dave Stevenson <[email protected]> | 2020-12-03 14:25:37 +0100 |
|---|---|---|
| committer | Maxime Ripard <[email protected]> | 2020-12-07 10:33:20 +0100 |
| commit | e02d5c43f2fdf7d71935de16e8c91b2cd3139f71 (patch) | |
| tree | 0a85302fe9faed34de649bc217fafdc2d4702bd4 /tools/perf/scripts/python/sctop.py | |
| parent | 51f4fcd9c4ea867c3b4fe58111f342ad0e80642a (diff) | |
drm/vc4: dsi: Correct DSI register definition
The DSI1_PHY_AFEC0_PD_DLANE1 and DSI1_PHY_AFEC0_PD_DLANE3 register
definitions were swapped, so trying to use more than a single data
lane failed as lane 1 would get powered down.
(In theory a 4 lane device would work as all lanes would remain
powered).
Correct the definitions.
Signed-off-by: Dave Stevenson <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/sctop.py')
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