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authorPotin Lai <[email protected]>2022-05-09 23:11:17 +0800
committerJoel Stanley <[email protected]>2022-05-19 16:57:45 +0930
commit9495c6d570600e275253036aa993735db8bd2451 (patch)
tree83885f8f863b633e26fb8055002d2f0bfbe9af39 /tools/perf/scripts/python/sctop.py
parent60280a214a41d896093daf162e7273338ebd396c (diff)
ARM: dts: aspeed: bletchley: add pca9536 node on each sled
Add an ioexp node on each sled baseed on DVT schematic, address at 0x41. P0: SLEDX_SWD_MUX P1: SLEDX_XRES_SWD_N P2: SLEDX_CLKREQ_N P3: SLEDX_PCIE_PWR_EN Signed-off-by: Potin Lai <[email protected]> Reviewed-by: Patrick Williams <[email protected]> Reviewed-by: Joel Stanley <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joel Stanley <[email protected]>
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