diff options
| author | Hawking Zhang <[email protected]> | 2020-12-01 23:13:12 +0800 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2020-12-23 15:04:14 -0500 |
| commit | 554bdbf6de74f5bd5852ce147c06172beb25a831 (patch) | |
| tree | 403701a97a11ba3c16510f547ac61639a7992d56 /tools/perf/scripts/python/sctop.py | |
| parent | 21822b6a968d948ae6cd09dfe7f4e43916d97b0e (diff) | |
drm/amdgpu: use cached ih rb control reg offsets for vega10
all the ih rb control register offsets are cached
at the beginning of ih_sw_init.
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Christian König <[email protected]>
Acked-by: Felix Kuehling <[email protected]>
Reviewed-by: Dennis Li <[email protected]>
Reviewed-by: Feifei Xu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/sctop.py')
0 files changed, 0 insertions, 0 deletions