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authorClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>2024-08-22 18:27:55 +0300
committerVinod Koul <vkoul@kernel.org>2024-08-30 13:33:44 +0530
commit4eae16375357a2a7e8501be5469532f7636064b3 (patch)
tree2d0d4221833d5de46511c368adc67f937a48a94b /tools/perf/scripts/python/sctop.py
parent0d5a213c2eae880e0f7f8bc252314bae194d68d8 (diff)
phy: renesas: rcar-gen3-usb2: Add support to initialize the bus
The Renesas RZ/G3S need to initialize the USB BUS before transferring data due to hardware limitation. As the register that need to be touched for this is in the address space of the USB PHY, and the UBS PHY need to be initialized before any other USB drivers handling data transfer, add support to initialize the USB BUS. As the USB PHY is probed before any other USB drivers that enables clocks and de-assert the reset signals and the BUS initialization is done in the probe phase, we need to add code to de-assert reset signal and runtime resume the device (which enables its clocks) before accessing the registers. As the reset signals are not required by the USB PHY driver for the other USB PHY hardware variants, the reset signals and runtime PM was handled only in the function that initialize the USB BUS. The PHY initialization was done right after runtime PM enable to have all in place when the PHYs are registered. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/r/20240822152801.602318-11-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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