scsi: smartpqi: Close write read holes

Insert a minimum 1 millisecond delay after writing to a register before
reading from it.

SIS and PQI registers that can be both written to and read from can return
stale data if read from too soon after having been written to.

There is no read/write ordering or hazard detection on the inbound path to
the MSGU from the PCIe bus, therefore reads could pass writes.

Link: https://lore.kernel.org/r/165730602555.177165.11181012469428348394.stgit@brunhilda
Reviewed-by: Scott Teel <[email protected]>
Signed-off-by: Mike McGowen <[email protected]>
Co-developed-by: Kevin Barnett <[email protected]>
Signed-off-by: Kevin Barnett <[email protected]>
Signed-off-by: Don Brace <[email protected]>
Signed-off-by: Martin K. Petersen <[email protected]>

0 files changed, 0 insertions, 0 deletions