diff options
author | Marek Szyprowski <[email protected]> | 2015-01-08 07:49:41 +0100 |
---|---|---|
committer | Russell King <[email protected]> | 2015-01-16 14:35:26 +0000 |
commit | 00218241aa0846e75d31b1dbadb5f8a76be1cc97 (patch) | |
tree | 98c70e0fe37d7f06e8d68ef47893004c271c4938 /tools/perf/scripts/python/sctop.py | |
parent | 944e9df1d4f71f946aa044abc00726346e3c597c (diff) |
ARM: 8258/1: l2c: use l2c_write_sec() for restoring latency and filter regs
All four register for latency and filter settings cannot be written in
non-secure mode and they should go through l2c_write_sec(). More on this
can be found in CoreLink Level 2 Cache Controller L2C-310 Technical
Reference Manual, 3.2. Register summary, table 3.1. This have been checked
the TRM for r3p3, but it should be uniform for all revisions.
Reported-by: Nishanth Menon <[email protected]>
Suggested-by: Tomasz Figa <[email protected]>
Signed-off-by: Marek Szyprowski <[email protected]>
Tested-by: Nishanth Menon <[email protected]>
Acked-by: Nishanth Menon <[email protected]>
Acked-by: Tony Lindgren <[email protected]>
Signed-off-by: Russell King <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/sctop.py')
0 files changed, 0 insertions, 0 deletions