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| author | Phil Edworthy <phil.edworthy@renesas.com> | 2022-05-18 16:01:05 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-06-06 11:13:30 +0200 |
| commit | efded37b426f4e1b7b004b1e9924ff4bf16ec0fd (patch) | |
| tree | 1a858638ed72338738e2b76f0cec18df5579bfca /tools/perf/scripts/python/sched-migration.py | |
| parent | e55c4481e71de79d0ef566a238332bd346cef6de (diff) | |
clk: renesas: r9a09g011: Add WDT clock and reset entries
Add WDT0 clock and reset entries to CPG driver.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Link: https://lore.kernel.org/r/20220518150105.48167-1-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/sched-migration.py')
0 files changed, 0 insertions, 0 deletions