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author | Werner Fischer <[email protected]> | 2023-12-13 10:45:25 +0100 |
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committer | Wim Van Sebroeck <[email protected]> | 2023-12-17 16:14:27 +0100 |
commit | d12971849d71781c1e4ffd1117d4878ce233d319 (patch) | |
tree | bd8346d06ae583ed1a8d10ccc0b6b0d1d0429cda /tools/perf/scripts/python/sched-migration.py | |
parent | ab6dea00fd6d148deecf2e8baaf0c110b35d7cea (diff) |
watchdog: it87_wdt: Keep WDTCTRL bit 3 unmodified for IT8784/IT8786
WDTCTRL bit 3 sets the mode choice for the clock input of IT8784/IT8786.
Some motherboards require this bit to be set to 1 (= PCICLK mode),
otherwise the watchdog functionality gets broken. The BIOS of those
motherboards sets WDTCTRL bit 3 already to 1.
Instead of setting all bits of WDTCTRL to 0 by writing 0x00 to it, keep
bit 3 of it unchanged for IT8784/IT8786 chips. In this way, bit 3 keeps
the status as set by the BIOS of the motherboard.
Watchdog tests have been successful with this patch with the following
systems:
IT8784: Thomas-Krenn LES plus v2 (YANLING YL-KBRL2 V2)
IT8786: Thomas-Krenn LES plus v3 (YANLING YL-CLU L2)
IT8786: Thomas-Krenn LES network 6L v2 (YANLING YL-CLU6L)
Link: https://lore.kernel.org/all/[email protected]/
Signed-off-by: Werner Fischer <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Guenter Roeck <[email protected]>
Signed-off-by: Wim Van Sebroeck <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/sched-migration.py')
0 files changed, 0 insertions, 0 deletions