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authorRussell King (Oracle) <[email protected]>2023-10-09 11:39:45 +0100
committerDavid S. Miller <[email protected]>2023-10-11 10:06:05 +0100
commita026809c261b7240a243ae1c2a7dccec3c316761 (patch)
tree23ccbd2a6553e9975029553145f60e9cc3b4fecd /tools/perf/scripts/python/sched-migration.py
parent9bae5b05502210f7fb5ac24874ec2e0747401b6b (diff)
net: dsa: vsc73xx: add phylink capabilities
Add phylink capabilities for vsc73xx. Although this switch driver does populates the .adjust_link method, dsa_slave_phy_setup() will still be used to create phylink instances for the LAN ports, although phylink won't be used for shared links. There are two different classes of switch - 5+1 and 8 port. The 5+1 port switches uses port indicies 0-4 for the user interfaces and 6 for the CPU port. The 8 port is confusing - some comments in the driver imply that port index 7 is used, but the driver actually still uses 6, so that is what we go with. Also, there appear to be no DTs in the kernel tree that are using the 8 port variety. It also looks like port 5 is always skipped. The switch supports 10M, 100M and 1G speeds. It is not clear whether all these speeds are supported on the CPU interface. It also looks like symmetric pause is supported, whether asymmetric pause is as well is unclear. However, it looks like the pause configuration is entirely static, and doesn't depend on negotiation results. So, let's do the best effort we can based on the information found in the driver when creating vsc73xx_phylink_get_caps(). Signed-off-by: Russell King (Oracle) <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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