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| author | Eugen Hristev <[email protected]> | 2022-05-03 10:44:21 +0200 |
|---|---|---|
| committer | Mauro Carvalho Chehab <[email protected]> | 2022-05-13 11:02:21 +0200 |
| commit | 9d5a3451e85802fc315d68b809b7b73471295f95 (patch) | |
| tree | 099cbd617a0a278473ded93549060a09afca71d6 /tools/perf/scripts/python/sched-migration.py | |
| parent | 4f564b92c3c7094f4ff2f29426a950acbb55b5d3 (diff) | |
media: dt-bindings: media: microchip,xisc: add bus-width of 14
The Microchip XISC supports a bus width of 14 bits.
Add it to the supported bus widths.
Signed-off-by: Eugen Hristev <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Hans Verkuil <[email protected]>
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/sched-migration.py')
0 files changed, 0 insertions, 0 deletions