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authorInochi Amaoto <[email protected]>2023-10-04 23:43:47 +0800
committerConor Dooley <[email protected]>2023-10-06 14:40:09 +0100
commit942e02e150721413b43068a8073819ad2b7d6314 (patch)
tree012019fe3d19745ee3b31cc2201c01ad62fcccce /tools/perf/scripts/python/sched-migration.py
parent4734449f73115c33733b136e225657107c03faf5 (diff)
dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi
The clint of Sophgo's sg2042 is based off IP designed by T-HEAD, and implements the not yet frozen ACLINT spec. This spec seems to be abandoned, and will not be frozen in the predictable future. Frozen specs required by the RISC-V maintainers before merging content relating to those extensions, therefore a generic compatible is not appropriate. Instead, add new vendor specific compatible strings to identify mswi of sg2042 clint. Signed-off-by: Inochi Amaoto <[email protected]> Signed-off-by: Chen Wang <[email protected]> [conor: re-wrote commit message to drop irrelevant sifive,clint discussion] Signed-off-by: Conor Dooley <[email protected]>
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