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| author | Doug Smythies <doug.smythies@gmail.com> | 2017-08-08 14:12:49 -0700 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2017-08-11 01:27:41 +0200 |
| commit | 8e2f3bce05e056575c2c84a344a8291fdabb5f21 (patch) | |
| tree | 0a68d4997d6c9d4e9b77faceca9132ab1d9120d8 /tools/perf/scripts/python/sched-migration.py | |
| parent | aae4e7a8bc44722fe70d58920a36916b1043195e (diff) | |
cpufreq: x86: Disable interrupts during MSRs reading
According to Intel 64 and IA-32 Architectures SDM, Volume 3,
Chapter 14.2, "Software needs to exercise care to avoid delays
between the two RDMSRs (for example interrupts)".
So, disable interrupts during reading MSRs IA32_APERF and IA32_MPERF.
See also: commit 4ab60c3f32c7 (cpufreq: intel_pstate: Disable
interrupts during MSRs reading).
Signed-off-by: Doug Smythies <dsmythies@telus.net>
Reviewed-by: Len Brown <len.brown@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/sched-migration.py')
0 files changed, 0 insertions, 0 deletions