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authorMaher Sanalla <[email protected]>2022-11-28 18:00:17 +0200
committerSaeed Mahameed <[email protected]>2023-01-10 21:24:39 -0800
commit8d231dbc3b10155727bcfa9e543d397ad357f14f (patch)
treed5ce74c6795a57eab9510deb6cdd68f0e66c2bc1 /tools/perf/scripts/python/sched-migration.py
parenta6f536063b69102adf3588fbc0bb4f08d6c8cb82 (diff)
net/mlx5: Expose shared buffer registers bits and structs
Add the shared receive buffer management and configuration registers: 1. SBPR - Shared Buffer Pools Register 2. SBCM - Shared Buffer Class Management Register Signed-off-by: Maher Sanalla <[email protected]> Reviewed-by: Moshe Shemesh <[email protected]> Signed-off-by: Saeed Mahameed <[email protected]>
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