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authorYanfei Xu <yanfei.xu@intel.com>2024-08-28 16:42:29 +0800
committerDave Jiang <dave.jiang@intel.com>2024-09-09 11:33:44 -0700
commit5c6e3d5a5da118be2ae074bd70d111994147c708 (patch)
tree6b72bd0fdc281b51468d5777b2fa8240d74d356f /tools/perf/scripts/python/sched-migration.py
parent55e268694e8b07026c88191f9b6949b6887d9ce3 (diff)
cxl/pci: Remove duplicated implementation of waiting for memory_info_valid
commit ce17ad0d5498 ("cxl: Wait Memory_Info_Valid before access memory related info") added another implementation, which is cxl_dvsec_mem_range_valid(), of waiting for memory_info_valid without realizing it duplicated wait_for_valid(). Remove wait_for_valid() and retain cxl_dvsec_mem_range_valid() as the former is hardcoded to check only the Memory_Info_Valid bit of DVSEC range 1, while the latter allows for selection between DVSEC range 1 or 2 via parameter. Suggested-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Yanfei Xu <yanfei.xu@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20240828084231.1378789-3-yanfei.xu@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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