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| author | Nandhini Srikandan <nandhini.srikandan@intel.com> | 2022-07-13 12:22:22 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2022-07-13 13:32:31 +0100 |
| commit | 51e41dc2f2bc7e7c8d5b8202a23eae3ee6056131 (patch) | |
| tree | 7b3f34c59d6e27e314577a31a8c13b2a098d9528 /tools/perf/scripts/python/sched-migration.py | |
| parent | 0d085723c637fd6929b8926a2963de1c2307cfa1 (diff) | |
spi: dw: Add support for master mode selection for DWC SSI controller
Add support to select the controller mode as master mode by setting Bit 31
of CTRLR0 register. This feature is supported for controller versions above
v1.02.
Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com>
Acked-by: Serge Semin <fancer.lancer@gmail.com>
Link: https://lore.kernel.org/r/20220713042223.1458-4-nandhini.srikandan@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/sched-migration.py')
0 files changed, 0 insertions, 0 deletions