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| author | Fenghua Yu <fenghua.yu@intel.com> | 2020-04-30 16:46:35 -0700 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2020-05-28 21:06:42 +0200 |
| commit | 429ac8b75a0b1c3478ffd584de8a63075cbe25e7 (patch) | |
| tree | 552b9400e50bd6acbb81f3b2b81d41818538b832 /tools/perf/scripts/python/sched-migration.py | |
| parent | 2ef96a5bb12be62ef75b5828c0aab838ebb29cb8 (diff) | |
x86/split_lock: Add Icelake microserver and Tigerlake CPU models
Icelake microserver CPU supports split lock detection while it doesn't
have the split lock enumeration bit in IA32_CORE_CAPABILITIES. Tigerlake
CPUs do enumerate the MSR.
[ bp: Merge the two model-adding patches into one. ]
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Link: https://lkml.kernel.org/r/1588290395-2677-1-git-send-email-fenghua.yu@intel.com
Diffstat (limited to 'tools/perf/scripts/python/sched-migration.py')
0 files changed, 0 insertions, 0 deletions