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authorTakeshi Kihara <takeshi.kihara.df@renesas.com>2019-03-25 17:35:50 +0100
committerGeert Uytterhoeven <geert+renesas@glider.be>2019-04-02 09:50:48 +0200
commit20cc05ba04a93f05d6c50789fe35d762a2db4e96 (patch)
treee1645087c864ccbb4eb065f4d09dadb998900464 /tools/perf/scripts/python/sched-migration.py
parent1addd6d568d02a9a1ce44307ec9c678e66e18c9e (diff)
clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor
Parameterise Z and Z2 clock fixed divisor to allow clocks with a fixed divisor other than 2, the value used by all such clocks supported to date. This is in preparation for supporting the Z2 clock on the R-Car E3 (r8a77990) SoC which has a fixed divisor of 4. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [simon: squashed several patches; rewrote changelog; added r8a774a1 change] Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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