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authorJani Nikula <[email protected]>2019-03-15 15:56:18 +0200
committerJani Nikula <[email protected]>2019-03-18 16:27:42 +0200
commit09b434d4f6d22e14500569e7e3f951e0eec4d496 (patch)
treeaf2d0bf787cf6ee53c14b7d66464f794cf92f3fa /tools/perf/scripts/python/sched-migration.py
parent6cffeb83c763235718102e9eca65e6452ac12ca7 (diff)
drm/i915: introduce REG_BIT() and REG_GENMASK() to define register contents
Introduce REG_BIT(n) to define register bits and REG_GENMASK(h, l) to define register bitfield masks. We define the above as wrappers to BIT() and GENMASK() respectively to force u32 type to go with our register size, and to add compile time checks on the bit numbers. The intention is that these are easier to get right and review against the spec than hand rolled masks. Convert power sequencer registers as an example. v4: - rebase v3: - rename macros to REG_BIT() and REG_GENMASK() to avoid underscore prefix and to be in line with kernel macros (Chris) - add compile time checks (Mika) v2: - rename macros to just _BIT() and _MASK() to reduce verbosity Cc: Chris Wilson <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Michal Wajdeczko <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: Ville Syrjälä <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Acked-by: Rodrigo Vivi <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/787307c0ba9bc23471e5ff1e454b8af35771fa37.1552657998.git.jani.nikula@intel.com
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