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| author | Peng Fan <peng.fan@nxp.com> | 2022-02-25 16:17:32 +0800 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@nxp.com> | 2022-03-04 17:06:29 +0200 |
| commit | 38ce00adc16319544c8c56edd36324d2c1b98a50 (patch) | |
| tree | 509d1699a6b06b9cd4f966dff59443b45f77369c /tools/perf/scripts/python/powerpc-hcalls.py | |
| parent | d25cbd3e392730f459f1fbf5f959c16b460a59ca (diff) | |
clk: imx8mn: remove SYS PLL 1/2 clock gates
Remove the PLL 1/2 gates as it make AMP clock management harder without
obvious benifit.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220225081733.2294166-3-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Diffstat (limited to 'tools/perf/scripts/python/powerpc-hcalls.py')
0 files changed, 0 insertions, 0 deletions