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authorBenjamin Herrenschmidt <[email protected]>2011-07-13 16:28:19 +1000
committerDave Airlie <[email protected]>2011-07-25 12:42:39 +0100
commit964f664520a4c6a247e2c9ff8b4481631cf746df (patch)
tree11bbb5e5f82b7ca236c0d40b76fd11f6efed634d /tools/perf/scripts/python/netdev-times.py
parentf1bece7fde9820a99c14d4db46ef071000e4ba47 (diff)
drm/radeon: Add a rmb() in IH processing
We should have a read memory barrier between reading the WPTR from memory and reading ring entries based on that value (ie, we need to ensure both loads are done in order by the CPU). It could be argued that the MMIO reads in r600_ack_irq() might be enough to get that barrier but I prefer keeping an explicit one just in case. [airlied: fix evergreen + r/w mixup] Signed-off-by: Benjamin Herrenschmidt <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
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