MIPS: pm-cps: Support CM3 changes to Coherence Enable Register

MIPS CM3 changed the management of coherence. Instead of a coherence
control register with a bitmask of coherent domains, CM3 simply has a
coherence enable register with a single bit to enable coherence of the
local core. Support this by clearing and setting this single bit to
disable / enable coherence.

Signed-off-by: Matt Redfearn <[email protected]>
Reviewed-by: Paul Burton <[email protected]>
Cc: Adam Buchbinder <[email protected]>
Cc: Tony Wu <[email protected]>
Cc: Masahiro Yamada <[email protected]>
Cc: Nikolay Martynov <[email protected]>
Cc: Kees Cook <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/14226/
Signed-off-by: Ralf Baechle <[email protected]>

0 files changed, 0 insertions, 0 deletions