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authorStephen Boyd <sboyd@kernel.org>2022-03-09 10:18:28 -0800
committerStephen Boyd <sboyd@kernel.org>2022-03-09 10:18:28 -0800
commit738e7891345fcc86ac06c0bf2aa57063e7085187 (patch)
tree7c9264f6b8d64530eb6e6ce9026e6bb5aefebca2 /tools/perf/scripts/python/netdev-times.py
parente783362eb54cd99b2cac8b3a9aeac942e6f6ac07 (diff)
parentb09c68dc57c9d44071d83bb935b733f53ea2b2b4 (diff)
Merge tag 'clk-imx-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx
Pull i.MX clk driver updates from Abel Vesa: - Add i.MXRT1050 clock driver and bindings - Add i.MX8DXL clock driver and bindings - Add i.MX93 clock driver and bindings - Remove SYS PLL 1/2 clock gates for i.MX8M* - Remove AUDIO MCLK ROOT from i.MX7D - Add fracn gppll clock type used by i.MX93 - Add new composite clock for i.MX93 - Add missing media mipi phy ref clock for i.MX8MP - Fix off by one in imx_lpcg_parse_clks_from_dt - Rework for the pll14xx * tag 'clk-imx-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux: (24 commits) clk: imx: pll14xx: Support dynamic rates clk: imx: pll14xx: Add pr_fmt clk: imx: pll14xx: explicitly return lowest rate clk: imx: pll14xx: name variables after usage clk: imx: pll14xx: consolidate rate calculation clk: imx: pll14xx: Use FIELD_GET/FIELD_PREP clk: imx: pll14xx: Drop wrong shifting clk: imx: pll14xx: Use register defines consistently clk: imx8mp: remove SYS PLL 1/2 clock gates clk: imx8mn: remove SYS PLL 1/2 clock gates clk: imx8mm: remove SYS PLL 1/2 clock gates clk: imx: add i.MX93 clk clk: imx: support fracn gppll clk: imx: add i.MX93 composite clk dt-bindings: clock: add i.MX93 clock definition dt-bindings: clock: Add imx93 clock support clk: imx: off by one in imx_lpcg_parse_clks_from_dt() dt-bindings: fsl: scu: add imx8dxl scu clock support clk: imx7d: Remove audio_mclk_root_clk clk: imx8mp: Add missing IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT clock ...
Diffstat (limited to 'tools/perf/scripts/python/netdev-times.py')
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