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| author | David Virag <virag.david003@gmail.com> | 2024-08-06 14:11:45 +0200 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2024-08-08 10:09:18 +0200 |
| commit | 59baa83e30f82b74b4c7dc07c20eac9899b6c0c6 (patch) | |
| tree | 4a33e3b5fecf50fa29f03659d6363147fe5231b5 /tools/perf/scripts/python/netdev-times.py | |
| parent | abf3a3ea9acb5c886c8729191a670744ecd42024 (diff) | |
dt-bindings: clock: exynos7885: Add CMU_TOP PLL MUX indices
Add indices for missing MUX clocks from PLLs in CMU_TOP.
Signed-off-by: David Virag <virag.david003@gmail.com>
Link: https://lore.kernel.org/r/20240806121157.479212-3-virag.david003@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/netdev-times.py')
0 files changed, 0 insertions, 0 deletions