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authorH Hartley Sweeten <[email protected]>2014-11-04 10:53:45 -0700
committerGreg Kroah-Hartman <[email protected]>2014-11-07 09:33:56 -0800
commit546bf3382e41b8a5a4c216ea7bdc0f517ce04e22 (patch)
treefe77f423d91e79a2e174164679060e185633aee2 /tools/perf/scripts/python/netdev-times.py
parent48d43be475e48f5673b89c1faa6f7855d25f9a85 (diff)
staging: comedi: addi_apci_3120: introduce apci3120_ns_to_timer()
The timer divisor calculations in this driver are over complicated. There are three timers on the board. They all use the same base clock with a fixed prescaler for each timer. The base clock used depends on the board version and type: APCI-3120 Rev A boards OSC = 14.29MHz base clock (~70ns) APCI-3120 Rev B boards OSC = 20MHz base clock (50ns) APCI-3001 boards OSC = 20MHz base clock (50ns) The prescalers for each timer are: Timer 0 CLK = OSC/10 Timer 1 CLK = OSC/1000 Timer 2 CLK = OSC/1000 Add a new member to the private data, 'osc_base', to hold the base clock time. Set this member during the board attach. Introduce a helper function to calculate the divisor needed to generate a nanosecond time with a given timer. Use the new helper function in the driver to clarify the code. Signed-off-by: H Hartley Sweeten <[email protected]> Reviewed-by: Ian Abbott <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
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