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| author | Aditya Swarup <[email protected]> | 2020-10-14 12:19:30 -0700 |
|---|---|---|
| committer | Lucas De Marchi <[email protected]> | 2020-10-15 14:14:30 -0700 |
| commit | 049c651b6d93839c74be5cb24708f1d8470ec60d (patch) | |
| tree | 5a2d1f649f44a710d5378eef4508f55425dc8ce8 /tools/perf/scripts/python/netdev-times.py | |
| parent | 240abb3c76ff4b469f91a753adb8426b77cab914 (diff) | |
drm/i915/dg1: Add DPLL macros for DG1
DG1 has 4 DPLLs where DPLL0 and DPLL1 drive DDIA/B and
DPLL2 and DPLL3 drive DDI-TC1/DDI-TC2.
Introduce DG1_DPLL_CFCRx() helper macros to configure
DPLL registers.
Bspec: 50288, 50299
Cc: Matt Roper <[email protected]>
Signed-off-by: Aditya Swarup <[email protected]>
Signed-off-by: Lucas De Marchi <[email protected]>
Reviewed-by: Matt Roper <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/netdev-times.py')
0 files changed, 0 insertions, 0 deletions