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authorVarshini Rajendran <varshini.rajendran@microchip.com>2024-07-29 12:37:37 +0530
committerClaudiu Beznea <claudiu.beznea@tuxon.dev>2024-08-07 19:16:46 +0300
commita402c663940dfeca22caa7390b9f35aee6925caf (patch)
tree60512789f6ce70271291ec76a7803f72880e0433 /tools/perf/scripts/python/net_dropmonitor.py
parent7f1bcdba5e28546aad4493e03f74abf65dc784ca (diff)
clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs
SAM9X7 SoC family supports different core output frequencies for different PLL IDs. To handle the same in the PLL driver, a separate parameter core_output is added. The sam9x60 and sama7g5 SoC PMC drivers are aligned to the PLL driver by adding the core output freq range in the PLL characteristics configurations. Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/20240729070737.1990756-1-varshini.rajendran@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
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