mtd: spi-nor: cadence-quadspi: add reset control

Get the reset control properties for the QSPI controller and bring them
out of reset. Most will have just one reset bit, but there is an additional
OCP reset bit that is used ECC. The OCP reset bit will also need to get
de-asserted as well. [1]

The reason this patch is needed is in the case where a bootloader leaves
the QSPI controller in a reset state, or a state where init cannot occur
successfully, the patch will put the QSPI controller into a clean state.

[1] https://www.intel.com/content/www/us/en/programmable/hps/arria-10/hps.html#reg_soc_top/sfo1429890575955.html

Suggested-by: Tien-Fong Chee <[email protected]>
Signed-off-by: Dinh Nguyen <[email protected]>
Reviewed-by: Vignesh Raghavendra <[email protected]>
[[email protected]: declare rstc and rstc_ocp on the same line]
Signed-off-by: Tudor Ambarus <[email protected]>

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